SN74ALS29854 Datasheet, PDF (1/9 Pages) Texas Instruments – 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

SN74ALS29854
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SDAS118C – FEBRUARY 1987 – REVISED JANUARY 1995
• Functionally Similar to AMD’s AM29854
• High-Speed Bus Transceiver With Parity
DW OR NT PACKAGE
(TOP VIEW)
Generator/Checker
• Parity-Error Flag With Open-Collector
Outputs
• Latch for Storing the Parity-Error Flag
• Package Options Include Plastic
OEA ₁
A1 ₂
A2 ₃
A3 4
A4 5
24 ^V_CC
23 ^B1
22 ^B2
21 B3
20 B4
Small-Outline (DW) Packages and Standard
A5 6
19 B5
Plastic (NT) 300-mil DIPs
A6 7
18 B6
description
A7 8
A8 9
17 B7
16 B8
The SN74ALS29854 is an 8-bit to 9-bit parity
transceiver designed for two-way communication
between data buses. When data is transmitted
ERR 10
CLR 11
GND 12
15 PARITY
14 OEB
13 LE
from the A bus to the B bus, a parity bit is
generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error
(ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs
can be used to disable the device so that the buses are effectively isolated.
A 9-bit parity generator / checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector ERR flag. ERR can be either passed, sampled, stored, or cleared from the latch using
the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.
The SN74ALS29854 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
OEB
OEA
INPUTS
CLR LE
Ai
∑ of Hs
Bi†
∑ of Ls
OUTPUT AND I/O
A
B PARITY ERR‡
L
H
X
X
Odd
Even
NA
NA
A
H
L
NA
H
L
X
L
NA
Odd
Even
B
NA
NA
H
L
H
L
H
H
NA
X
X
NA
NA
N-1
X
X
L
H
X
X
X
NA
NA
H
H
H
X
NC
H
H
L
X
H
X
L
L Odd
X
Z
Z
Z
H
L
X
L H Even
H
L
L
X
X
Odd
Even
NA
NA
A
L
H
NA
NA = not applicable, NC = no change, X = don’t care
† _{Summation of high-level inputs includes PARITY along with Bi inputs.}
‡ _{Output states shown assume ERR was previously high.}
§ _{In this mode, ERR, when enabled, shows inverted parity of the A bus.}
OPERATION
A data to B bus and generate parity
B data to A bus and check parity
Store error flag
Clear error-flag register
Isolation§
A data to B bus and generate inverted
parity
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1995, Texas Instruments Incorporated
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