SN74AHCT125-EP Datasheet, PDF (1/12 Pages) Texas Instruments – QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SN74AHCT125ĆEP
QUADRUPLE BUS BUFFER GATE
WITH 3ĆSTATE OUTPUTS
SCLS549 − DECEMBER 2003
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Inputs Are TTL-Voltage Compatible
D OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1Y 3
2OE 4
2A ⁵
2Y ⁶
GND ⁷
14 V_CC
13 4OE
12 4A
11 4Y
10 3OE
9 _3A
8 _3Y
description/ordering information
The SN74AHCT125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each
output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate
passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C
SOIC − D
TSSOP − PW
Tape and reel
Tape and reel
SN74AHCT125QDREP AHCT125QEP
SN74AHCT125QPWREP HB125EP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
1