SN74AHC2G125 Datasheet, PDF (1/6 Pages) Texas Instruments – DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

D EPIC™ (Enhanced-Performance Implanted
CMOS) Process
D Operating Range 2-V to 5.5-V V_CC
D Packaged in Plastic Small-Outline
Transistor Package
description
SN74AHC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCLS439A – SEPTEMBER 1999 – REVISED NOVEMBER 1999
DCT PACKAGE
(TOP VIEW)
1OE 1
1A 2
2Y 3
GND 4
8 V_CC
7 2OE
6 1Y
5 2A
The SN74AHC2G125 is a dual bus buffer gate/line driver with 3-state outputs. The outputs are disabled when
the output-enable (OE) input is high. When OE is low, true data is passed from the A input to the Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74AHC2G125 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
logic symbol^†
1
1OE
EN
2
1A
7
2OE
5
2A
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.}
6
1Y
3
2Y
logic diagram (positive logic)
1
1OE
2
1A
6
1Y
7
2OE
5
2A
3
2Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright © 1999, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1