SN74AC373-EP Datasheet, PDF (1/9 Pages) Texas Instruments – OCTAL D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−55°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D 2-V to 6-V V_CC Operation
D Inputs Accept Voltages to 6 V
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SN74AC373ĆEP
OCTAL DĆTYPE TRANSPARENT LATCH
WITH 3ĆSTATE OUTPUTS
SCAS725 − OCTOBER 2003
D Max t_pd of 9.5 ns at 5 V
D 3-State Noninverting Outputs Drive Bus
Lines Directly
D Full Parallel Access for Loading
DW PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
description/ordering information
This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow
the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
in bus-organized systems without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−55°C to 125°C SOIC − DW
Tape and reel SN74AC373MDWREP SAC373MEP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
1