SN74ABTH32543-EP Datasheet, PDF (1/10 Pages) Texas Instruments – 36-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

D Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
–55°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product Change Notification
D Qualification Pedigree^†
D Member of the Texas Instruments
Widebus+ Family
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SN74ABTH32543-EP
36-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS757 – AUGUST 2002
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 5 V, T_A = 25°C
D High-Impedance State During Power Up
and Power Down
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D High-Drive Outputs (–32-mA I_OH, 64-mA I_OL)
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D 100-Pin Plastic Thin Quad Flat (PZ)
Package With 14- × 14-mm Body Using
0.5-mm Lead Pitch
description
The ’ABTH32543 is a 36-bit registered transceiver that contains two sets of D-type latches for temporary storage
of data flowing in either direction. This device can be used as two 18-bit transceivers or one 36-bit transceiver.
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each
register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and
OEBA inputs.
When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V_CC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–55°C to 125°C LQFP – PZ SN74ABTH32543MPZEP 74ABTH32543MEP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB}
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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