SN74ABT5402 Datasheet, PDF (1/11 Pages) Texas Instruments – 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS

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• Output Ports Have 25-Ω Series Resistors,
So No External Resistors Are Required
• State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce)
< 1 V at V_CC = 5 V, T_A = 25°C
• Typical V_OLV (Output Undershoot)
< 0.5 V at V_CC = 5 V, T_A = 25°C
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK) and DIPs (JT)
description
These 12-bit buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all 12 outputs are in the
high-impedance state.
The outputs, which are designed to source or sink
up to 12 mA, include 25-Ω series resistors to
reduce overshoot and undershoot.
To ensure the high-impedance state during power
up or power down, OE should be tied to V_CC
through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking
capability of the driver.
The SN54ABT5402 is characterized for operation
over the full military temperature range of − 55°C
to 125°C. The SN74ABT5402 is characterized for
operation from −40°C to 85°C.
SN54ABT5402, SN74ABT5402
12ĆBIT LINE/MEMORY DRIVERS
WITH 3ĆSTATE OUTPUTS
SCBS100B − JANUARY 1992 − REVISED JULY 1994
SN54ABT5402 . . . JT PACKAGE
SN74ABT5402 . . . DW PACKAGE
(TOP VIEW)
Y1 1
Y2 2
Y3 3
Y4 4
Y5 5
Y6 6
GND 7
Y7 8
Y8 9
Y9 10
Y10 11
Y11 12
Y12 13
OE1 14
28 D1
27 D2
26 D3
25 D4
24 D5
23 D6
22 D7
21 V_CC
20 D8
19 D9
18 D10
17 D11
16 D12
15 OE2
SN54ABT5402 . . . FK PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
D3 ₅
25 ^D10
D2 ₆
24 ^D11
D1 ₇
23 D12
Y1 ₈
22 OE2
Y2 ₉
21 OE1
Y3 _{1 0}
20 Y12
Y4 ₁₁
19 Y11
12 13 14 15 16 17 18
FUNCTION TABLE
INPUTS
OE1 OE2 D
OUTPUT
Y
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
Copyright  1994, Texas Instruments Incorporated
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