SN65MLVD040 Datasheet, PDF (1/29 Pages) Texas Instruments – 4-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS

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SN65MLVD040
SLLS902 – FEBRUARY 2010
4-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
Check for Samples: SN65MLVD040
FEATURES
1
•2 Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers and Receivers for Signaling Rates⁽¹⁾ Up
to 250 Mbps; Clock Frequencies Up to
125 MHz
• Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Data Interchange
• Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
• –1 V to 3.4 V Common-Mode Voltage Range
Allows Data Transfer With 2 V of Ground Noise
• Bus Pins High Impedance When Driver
Disabled or V_CC ≤ 1.5 V
• Independent Enables for each Driver and
Receiver
• Enhanced ESD Protection: 7 kV HBM on all
Pins
• 48 pin 7 X 7 QFN (RGZ)
• M-LVDS Bus Power Up/Down Glitch Free
APPLICATIONS
• Parallel Multipoint Data and Clock
Transmission Via Backplanes and Cables
• Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485
• Cellular Base Stations
• Central-Office Switches
• Network Switches and Routers⁽¹⁾
1DE
1D
1FSEN
1R
LOGIC DIAGRAM (POSITIVE LOGIC)
SN65MLVD 040
Channel 1
1A
1B
1RE
PDN
2DE - 4E ₃
2D - 4D ₃
2FSEN –
4FSEN 3
2R - 4R ₃
2RE – 4RE ₃
Channels 2 - 4
2A - 4A
2B - 4B
(1) The signaling rate of a line, is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
DESCRIPTION
The SN65MLVD040 provides four half-duplex transceivers for transmitting and receiving Multipoint-Low-Voltage
Differential Signals in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at
signaling rates up to 250 Mbps. The driver outputs have been designed to support multipoint buses presenting
loads as low as 30-Ω and incorporates controlled transition times to allow for stubs off of the backplane
transmission line.
The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers have
thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2
receivers implement a failsafe by using an offset threshold. The xFSEN pins is used to select the Type-1 and
Type-2 receiver for each of the channels. In addition, the driver rise and fall times are between 1 ns and 2 ns,
complying with the M-LVDS standard to provide operation at 250 Mbps while also accommodating stubs on the
bus. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current
surges. The M-LVDS standard allows for 32 nodes on the bus providing a high-speed replacement for RS-485
where lower common-mode can be tolerated or when higher signaling rates are needed.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated