SN65LVDS95-EP Datasheet, PDF (1/15 Pages) Texas Instruments – LVDS SERDES TRANSMITTER

SN65LVDS95ĆEP
LVDS SERDES TRANSMITTER
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D 21:3 Data Channel Compression at up to
1.36 Gigabits per Second Throughput
D Suited for Point-to-Point Subsystem
Communication With Very Low EMI
D 21 Data Channels Plus Clock in
Low-Voltage TTL and 3 Data Channels Plus
Clock Out Low-Voltage Differential
D Operates From a Single 3.3-V Supply and
250 mW (Typ)
D 5-V Tolerant Data Inputs
D ’LVDS95 Has Rising Clock Edge Triggered
Inputs
D Bus Pins Tolerate 6-kV HBM ESD
D Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
D Consumes <1 mW When Disabled
D Wide Phase-Lock Input Frequency Range
20 MHz to 68 MHz
D No External Components Required for PLL
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SGLS206A − OCTOBER 2003 − REVISED SEPTEMBER 2009
D Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
D Industrial Temperature Qualified
T_A = −40°C to 85°C
D Replacement for the National DS90CR215
DGG PACKAGE
(TOP VIEW)
D4 1
V_CC 2
D5 3
D6 4
GND 5
D7 6
D8 7
V_CC 8
D9 9
D10 10
GND 11
D11 12
D12 13
NC 14
D13 15
D14 16
GND 17
D15 ¹⁸
D16 ¹⁹
D17 ²⁰
V_CC ²¹
D18 ²²
D19 ²³
GND ²⁴
48 D3
47 D2
46 GND
45 D1
44 D0
43 NC
42 LVDSGND
41 Y0M
40 Y0P
39 Y1M
38 Y1P
37 LVDSV_CC
36 LVDSGND
35 Y2M
34 Y2P
33 CLKOUTM
32 CLKOUTP
31 _LVDSGND
30 _PLLGND
29 _PLLVCC
28 _PLLGND
27 _SHTDN
26 _CLKIN
25 _D20
description/ordering information
The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out
shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single
integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted
over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.
When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising
edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to
serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT)
are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
1