SN65LVDS93_15 Datasheet, PDF (1/19 Pages) Texas Instruments – LVDS SERDES TRANSMITTER

SN65LVDS93
www.ti.com ................................................................................................................................................................. SLLS302G – MAY 1998 – REVISED MAY 2009
LVDS SERDES TRANSMITTER
FEATURES
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• 28:4 Data Channel Compression at up to
1.904 Gigabits per Second Throughput
• Suited for Point-to-Point Subsystem
Communication With Very Low EMI
• 28 Data Channels Plus Clock in Low-Voltage
TTL and 4 Data Channels Plus Clock Out
Low-Voltage Differential
• Selectable Rising or Falling Clock Edge
Triggered Inputs
• Bus Pins Tolerate 6-kV HBM ESD
• Operates From a Single 3.3-V Supply and
250 mW (Typ)
• 5-V Tolerant Data Inputs
• Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
• Consumes <1 mW When Disabled
• Wide Phase-Lock Input Frequency Range
20 MHz to 68 MHz
• No External Components Required for PLL
• Outputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
• Industrial Temperature Qualified T_A = –40°C
to 85°C
• Replacement for the DS90CR285
DESCRIPTION
The SN65LVDS93 LVDS serdes (serializer/
deserializer) transmitter contains four 7-bit parallel-
load serial-out shift registers, a 7× clock synthesizer,
and five low-voltage differential signaling (LVDS)
drivers in a single integrated circuit. These functions
allow 28 bits of single-ended LVTTL data to be
synchronously transmitted over five balanced-pair
conductors for receipt by a compatible receiver, such
as the SN65LVDS94.
When transmitting, data bits D0 through D27 are
each loaded into registers upon the edge of the input
clock signal (CLKIN). The rising or falling edge of the
clock can be selected via the clock select (CLKSEL)
pin. The frequency of CLKIN is multiplied seven times
and then used to serially unload the data registers in
7-bit slices. The four serial streams and a
phase-locked clock (CLKOUT) are then output to
LVDS output drivers. The frequency of CLKOUT is
the same as the input clock, CLKIN.
DGG PACKAGE
(TOP VIEW)
V_{CC 1}
D5 2
D6 3
D7 4
GND 5
D8 6
D9 7
D10 8
V_CC 9
D11 10
D12 11
D13 12
GND 13
D14 14
D15 15
D16 16
CLKSEL 17
D17 18
D18 19
D19 20
GND 21
D20 22
D21 ²³
D22 ²⁴
D23 ²⁵
V_CC ²⁶
D24 ²⁷
D25 ²⁸
56 ^D4
55 D3
54 D2
53 GND
52 D1
51 D0
50 D27
49 LVDSGND
48 Y1M
47 Y1P
46 Y2M
45 Y2P
44 LVDSV_CC
43 LVDSGND
42 Y3M
41 Y3P
40 CLKOUTM
39 CLKOUTP
38 Y4M
37 Y4P
36 LVDSGND
35 PLLGND
34 _PLLVCC
33 _PLLGND
32 _SHTDN
31 _CLKIN
30 _D26
29 _GND
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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