SN65LVDS387_16 Datasheet, PDF (1/39 Pages) Texas Instruments – High-Speed Differential Line Drivers

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SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
SLLS362G – SEPTEMBER 1999 – REVISED JANUARY 2016
SNx5LVDS3xx High-Speed Differential Line Drivers
1 Features
•1 Four ('391), Eight ('389), or Sixteen ('387) Line
Drivers Meet or Exceed the Requirements of ANSI
EIA/TIA-644 Standard
• Designed for Signaling Rates Up to 630 Mbps
With Very Low Radiation (EMI)
• Low-Voltage Differential Signaling With Typical
Output Voltage of 350 mV and a 100-Ω Load
• Propagation Delay Times Less Than 2.9 ns
• Output Skew Is Less Than 150 ps
• Part-to-Part Skew Is Less Than 1.5 ns
• 35-mW Total Power Dissipation in Each Driver
Operating at 200 MHz
• Driver Is High-Impedance When Disabled or With
V_CC < 1.5 V
• SN65' Version Bus-Pin ESD Protection Exceeds
15 kV
• Packaged in Thin Shrink Small-Outline Package
With 20-mil Pin Pitch
• Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V
Tolerant
2 Applications
• Wireless Infrastructure
• Telecom Infrastructure
• Printer
3 Description
This family of 4, 8, and 16 differential line drivers
implements the electrical characteristics of low-
voltage differential signaling (LVDS). This signaling
technique lowers the output voltage levels of 5-V
differential standard levels (such as EIA/TIA-422B) to
reduce the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the 16
current-mode drivers will deliver a minimum
differential output voltage magnitude of 247 mV into a
100-Ω load when enabled.
Device Information⁽¹⁾
PART NUMBER PACKAGE
BODY SIZE (NOM)
SN65LVDS387
TSSOP (64)
17.00 mm × 6.10 mm
SN75LVDS387
TSSOP (38)
9.70 mm × 4.40 mm
SN65LVDS389
SOIC (16)
TSSOP (16)
9.90 mm × 3.91 mm
5.00 mm × 4.40 mm
SN75LVDS389
TSSOP (64)
17.00 mm × 6.10 mm
SN65LVDS391
TSSOP (38)
9.70 mm × 4.40 mm
SN75LVDS391
SOIC (16)
TSSOP (16)
9.90 mm × 3.91 mm
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Host
Controller
Host
Power
DBn
DBn–1
DBn–2
DBn–3
Balanced Interconnect
Power
T
T
T
T
Target
DBn
DBn–1
DBn–2
DBn–3
Target
Controller
DB2
DB1
DB0
TX Clock
T
DB2
T
DB1
T
DB0
T
RX Clock
SN65LVDS387 or 389
1
Indicates twisting of the
conductors.
LVDS Receiver(s)
Indicates the line termination
T _circuit.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.