SN65LVDS310 Datasheet, PDF (1/32 Pages) Texas Instruments – PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

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SN65LVDS310
SLLS836 – MAY 2007
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
FEATURES
• Serial Interface Technology
• Compatible With FlatLink™ 3G Transmitters
(E.g., SN65LVDS305 or SN65LVDS307)
• Supports Video Interfaces up to 24-Bit RGB
Data and 3 Control Bits Received Over One
SubLVDS Differential Data Line
• SubLVDS Differential Voltage Levels
• Up to 405-Mbps Data Throughput
• Three Operating Modes to Conserve Power
– Active mode QVGA: 17 mW
– Typical Shutdown: 0.7 µW
– Typical Standby Mode: 67 µW Typical
• ESD Rating > 4 kV (HBM)
• Pixel-Clock Range of 4 MHz–15 MHz
• Failsafe on All CMOS Inputs
• Packaged in 4-mm × 4-mm MicroStar
Junior™µBGA^® With 0,5-mm Ball Pitch
• Very Low EMI
APPLICATIONS
• Small Low-Emission Interface Between
Graphics Controller and LCD Display
• Mobile Phones and Smart Phones
• Portable Multimedia Players
DESCRIPTION
The SN65LVDS310 receiver deserializes FlatLink
3G-compliant serial input data to 27 parallel data
outputs. The SN65LVDS310 receiver contains one
shift register to load 30 bits from one serial input and
latches the 24 pixel bits and 3 control bits out to the
parallel CMOS outputs after checking the parity bit. If
a parity error is detected, the data output bus
disregards the newly received pixel. Instead, the last
data word is held on the output bus for another clock
cycle.
The serial data and clock are received via
sub-low-voltage differential signalling (SubLVDS)
lines. The SN65LVDS310 supports three operating
power modes (shutdown, standby, and active) to
conserve power.
When receiving, the PLL locks to the incoming clock,
CLK, and generates an internal high-speed clock at
the line rate of the data lines. The data is serially
loaded into a shift register using the internal
high-speed clock. The deserialized data is presented
on the parallel output bus with a recreation of the
pixel clock, PCLK, generated from the internal
high-speed clock. If no input CLK signal is present,
the output bus is held static with PCLK and DE held
low, while all other parallel outputs are pulled high.
The F/S conrol input selects between a slow CMOS
bus output rise time for best EMI and power
consumption and a fast CMOS output for increased
speed or higher-load designs.
Flatlinkä3G
123
456
789
*^0#
LCD
Driver
LVDS310
CLK DATA
LVDS307
Application
Processor
with
RGB
Video
Interface
M0056-04
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink, MicroStar Junior are trademarks of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated