SN65LVDS150_09 Datasheet, PDF (1/18 Pages) Texas Instruments – MuxIt PLL FREQUENCY MULTIPLIER

SN65LVDS150
www.ti.com
MuxIt™ PLL FREQUENCY MULTIPLIER
SLLS443 – DECEMBER 2000
FEATURES
• A Member of the MuxIt™ Serializer-
Deserializer Building-Block Chip Family
• Pin Selectable Frequency Multiplier Ratios
Between 4 and 40
• Input Clock Frequencies From 5 to 50 MHz
• Multiplied Clock Frequencies up to
400 MHz
• Internal Loop Filters and Low PLL-Jitter of
20 ps RMS Typical at 200 MHz
• LVDS Compatible Differential Inputs and
Outputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644-A
• LVTTL Compatible Inputs Are 5 V Tolerant
• LVDS Inputs and Outputs ESD Protection
Exceeds 12 kV HBM
• Operates From a Single 3.3 V Supply
• Packaged in 28-Pin Thin Shrink Small-Outline
Package With 26 mil Terminal Pitch
SN65LVDS150
PW PACKAGE
(Marked as 65LVDS150)
V_{CC 1}
CRI+ 2
CRI– 3
V_T 4
GND 5
M1 6
M2 7
M3 8
M4 9
M5 10
BSEL 11
GND 12
LCRO– 13
LCRO+ 14
28 ^NC
27 NC
26 NC
25 VCC
24 GND
23 NC
22 GND
21 NC
20 MCO+
19 MCO–
18 GND
17 EN
16 LCRO_EN
15 LVO
NC – No internal connection
DESCRIPTION
The MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers
and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of
differential transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or
LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for
higher transmission efficiencies than with other existing fixed ratio solutions. Muxlt utilizes the LVDS
(TIA/EIA-644) low voltage differential signaling technology for communications between the data source and data
destination.
The MuxIt family initially includes three devices supporting simplex communications; The SN65LVDS150 Phase
Locked Loop-Frequency Multiplier, The SN65LVDS151 Serializer-Transmitter, and The SN65LVDS152
Receiver-Deserializer.
The SN65LVDS150 is a PLL based frequency multiplier designed for use with the other members of the MuxIt
family of serializers and deserializers. The frequency multiplication ratio is pin selectable over a wide range of
values from 4 through 40 to accommodate a broad spectrum of user needs. No external filter components are
needed. A PLL lock indicator output is available which may be used to enable link data transfers.
The design of the SN65LVDS150 allows it to be used at either the transmit end or the receive end of the MuxIt
serial link. The differential clock reference input (CRI) is driven by the system's parallel data clock when at the
source end of the link, or by the link clock when at the destination end of the link. The differential clock reference
input may be driven by either an LVDS differential signal, or by a single ended clock of either polarity. For
single-ended use the nonclocked input is biased to the logic threshold voltage. A V_CC/2 threshold reference, VT,
is provided on a pin adjacent the differential CRI pins for convenience when the input is used in a single-ended
mode.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MuxIt is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated