SN65LVCP114 Datasheet, PDF (1/30 Pages) Texas Instruments – 14.2-Gbps Quad 1:2-2:1 MUX, Linear-Redriver With Signal Conditioning

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SN65LVCP114
SLLSEA8 – JANUARY 2012
14.2-Gbps Quad 1:2-2:1 MUX, Linear-Redriver With Signal Conditioning
Check for Samples: SN65LVCP114
FEATURES
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• Quad 2:1 Mux / 1:2 Demux
• Multi-Rate Operation up to 14.2 Gbps Serial
Data Rate
• Linear Receiver Equalization Which Increases
Margin at System Level of Decision Feedback
Equalizer
• Bandwidth: 18 GHz, Typical
• Per-Lane P/N Pair Inversion
• Port or Single Lane Switching
• Low Power: 150 mW/Channel, Typical
• Loopback Mode on All Three Ports
• I²C Control in Addition to GPIO
• DIAG Mode That Outputs Data of Line Side
Port to Both Fabric Side Ports
• 2.5-V/3.3-V Single Power Supply
• PBGA Package 12-mm × 12-mm × 1-mm,
0.8-mm Terminal Pitch
• Excellent Impedance Matching to 100-Ω PCB
Transmission Lines
• Small Package Size Provides Board Real
Estate Saving
• Adjustable Output Swing Provides Flexible
EMI and Crosstalk Control
• Low Power
• Supports 10GBASE-KR Applications With
Ability to Transparency for Link Training
APPLICATIONS
• High-Speed Redundancy Switch in Telecom
and Data Communication
• Backplane Interconnect for 10G-KR, 16GFC
DESCRIPTION
The SN65LVCP114 is an asynchronous, protocol-agnostic, low-latency QUAD mux, linear-redriver optimized for
use in systems operating at up to 14.2 Gbps. The device linearly compensates for channel loss in backplane and
active-cable applications. The architecture of SN65LVCP114 linear-redriver is designed to work effectively with
ASIC or FPGA products implementing digital equalization using decision feedback equalizer (DFE) technology.
The SN65LVCP114 mux, linear-redriver preserves the integrity (composition) of the received signal, ensuring
optimum DFE and system performance. The SN65LVCP114 provides a low-power mux-demux, linear-redriver
solution while at the same time extending the effectiveness of DFE.
SN65LVCP114 is configurable via GPIO or an I²C interface.
A single 2.5-V or 3.3-V power supply supports the operation of the SN65LVCP114.
The SN65LVCP114 is packaged in a 12-mm × 12-mm × 1-mm PBGA package with 0.8-mm pitch.
The SN65LVCP114 has three ports; each port is a quad lane. The switch logic of SN65LVCP114 can be
implemented to support a 2:1 MUX per lane, 1:2 DEMUX per lane, and independent lane switching. The receive
equalization can be independently programmed for each of the ports. The SN65LVCP114 supports loopback on
all three ports.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated