SN65LBC180-Q1 Datasheet, PDF (1/17 Pages) Texas Instruments – LOW-POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIR

SN65LBC180ĆQ1
LOWĆPOWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIR
D Qualified for Automotive Applications
D Designed for High-Speed Multipoint Data
Transmission Over Long Cables
D Operate With Pulse Durations as Low
as 30 ns
D Low Supply Current . . . 5 mA Max
D Meet or Exceed the Requirements of ANSI
Standard RS-485 and ISO 8482:1987(E)
D 3-State Outputs for Party-Line Buses
D Common-Mode Voltage Range of
−7 V to 12 V
D Thermal Shutdown Protection Prevents
Driver Damage From Bus Contention
D Positive and Negative Output Current
Limiting
D Pin Compatible With the SN75ALS180
description
The SN65LBC180 differential driver and receiver
pair is a monolithic integrated circuit designed for
bidirectional data communication over long
cables that take on the characteristics of
transmission lines. It is a balanced, or differential,
voltage mode device that meets or exceeds the
requirements of industry standards ANSI RS-485
and ISO 8482:1987(E). The device is designed
using TI’s proprietary LinBiCMOS with the low
power consumption of CMOS and the precision
and robustness of bipolar transistors in the same
circuit.
The SN65LBC180 combines a differential line
driver and receiver with 3-state outputs and
operates from a single 5-V supply. The driver and
receiver have active-high and active-low enables,
respectively, which can be externally connected to
function as a direction control. The driver
differential outputs and the receiver differential
inputs are connected to separate terminals for
full-duplex operation and are designed to present
minimum loading to the bus whether disabled or
powered off (V_CC = 0). This part features a wide
common-mode voltage range making it suitable
for point-to-point or multipoint data-bus
applications.
SGLS251A − JULY 2004 − REVISED JUNE 2008
D PACKAGE
(TOP VIEW)
NC ₁
R₂
RE 3
DE 4
D5
GND 6
GND 7
14 V_CC
13 V_CC
12 A
11 B
10 Z
9Y
8 NC
NC −No internal connection
Function Tables
DRIVER
INPUT
D
H
L
X
ENABLE
DE
H
H
L
OUTPUTS
YZ
HL
LH
ZZ
RECEIVER
DIFFERENTIAL INPUTS
A−B
VID ≥ 0.2 V
−0.2 V < VID < 0.2 V
VID ≤ − 0.2 V
X
Open circuit
ENABLE
RE
L
L
L
H
L
OUTPUT
R
H
?
L
Z
H
H = high level, L = low level, ? = indeterminate, X = irrelevant,
Z = high impedance (off)
logic diagram (positive logic)
4
DE
5
D
3
RE
2
R
9
Y
10
Z
12
A
11
B
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2008 Texas Instruments Incorporated
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