SN65LBC176A-EP Datasheet, PDF (1/17 Pages) Texas Instruments – DIFFERENTIAL BUS TRANSCEIVER

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D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 125°C and −55°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product Change Notification
D Qualification Pedigree^†
D High-Speed Low-Power LinBiCMOS
Circuitry Designed for Signaling Rates^‡ Up
to 30 Mbps
D Bus-Pin ESD Protection Exceeds 12-kV
HBM
D Compatible With ANSI Standard
TIA/EIA-485-A and ISO 8482:1987(E)
D Low Skew
D Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D Low Disabled Supply Current
Requirements . . . 700 µA Maximum
D Common-Mode Voltage Range of −7 V
to 12 V
D Thermal-Shutdown Protection
D Driver Positive and Negative Current
Limiting
D Open-Circuit Fail-Safe Receiver Design
D Receiver Input Sensitivity . . . ± 200 mV Max
D Receiver Input Hysteresis . . . 50 mV Typ
D Glitch-Free Power-Up and Power-Down
Protection
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
‡ _{Signaling rate by TIA/EIA-485-A definition restrict transition times}
to 30% of the bit length, and much higher signaling rates may be
achieved without this requirement as displayed in the TYPICAL
CHARACTERISTICS of this device.
SN65LBC176AĆEP
DIFFERENTIAL BUS TRANSCEIVER
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SGLS151C − DECEMBER 2002 − REVISED JULY 2004
D Package
(TOP VIEW)
R₁
RE 2
DE 3
D4
8 V_CC
7B
6A
5 GND
logic diagram (positive logic)
3
DE
4
D
2
RE
1
R
6
A
7B
Bus
Function Tables
INPUT
D
H
L
X
Open
DRIVER
ENABLE
DE
H
H
L
H
OUTPUTS
AB
HL
LH
ZZ
HL
RECEIVER
DIFFERENTIAL INPUTS
VA −VB
VID ≥ 0.2 V
−0.2 V < VID < 0.2 V
VID ≤ − 0.2 V
X
Open
ENABLE
RE
L
L
L
H
L
OUTPUT
R
H
?
L
Z
H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS and LinASIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2004, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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