SN65DSI85-Q1 Datasheet, PDF (1/7 Pages) Texas Instruments – MIPI DSI Bridge to FlatLink LVDS Dual-Channel DSI to Dual-Link LVDS Bridge

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SN65DSI85-Q1 MIPI® DSI Bridge to FlatLink™ LVDS
Dual-Channel DSI to Dual-Link LVDS Bridge
SN65DSI85-Q1
SLLSEJ4 – JULY 2016
1 Features
•1 Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C6
• Implements MIPI^® D-PHY Version 1.00.00
Physical Layer Front-End and Display Serial
Interface (DSI) Version 1.02.00
• Dual-Channel DSI Receiver Configurable for One,
Two, Three, or Four D-PHY Data Lanes Per
Channel Operating up to 1 Gbps Per Lane
• Supports 18-bpp and 24-bpp DSI Video Packets
with RGB666 and RGB888 Formats
• Suitable for 60-fps WQXGA 2560 × 1600
Resolution at 18 bpp and 24 bpp Color, and
WUXGA 1920 × 1200 Resolution With 3D
Graphics at 60 fps (120 fps Equivalent)
• MIPI Front-End Configurable for Single-Channel
or Dual-Channel DSI Configurations
• FlatLink™ Output Configurable for Single-Link or
Dual-Link LVDS
• Supports Dual-Channel DSI ODD or EVEN and
LEFT or RIGHT Operating Modes
• Supports Two Single-Channel DSI to Two Single-
Link LVDS Operating Mode
• LVDS Output-Clock Range of 25 MHz to 154 MHz
in Dual-Link or Single-Link Mode
• LVDS Pixel Clock May be Sourced from Free-
Running Continuous D-PHY Clock or External
Reference Clock (REFCLK)
• 1.8 V Main V_CC Power Supply
• Low Power Features Include SHUTDOWN Mode,
Reduced LVDS Output Voltage Swing, Common
Mode, and MIPI Ultra-Low Power State (ULPS)
Support
• LVDS Channel SWAP, LVDS PIN Order Reverse
Feature for Ease of PCB Routing
• Packaged in 64-pin 10 mm × 10 mm HTQFP
(PAP) PowerPAD™ IC Package
2 Applications
• Infotainment Head Unit With Integrated Display
• Infotainment Head Unit With Remote Display
• Infotainment Rear-Seat Entertainment
• Hybrid Automotive Cluster
• Portable Navigation Device (PND)
• Industrial Human Machine Interface (HMI) and
Displays
3 Description
The SN65DSI85-Q1 DSI-to-FlatLink bridge features a
dual-channel MIPI D-PHY receiver front-end
configuration with four lanes per channel operating at
1 Gbps per lane and a maximum input bandwidth of 8
Gbps. The bridge decodes MIPI DSI 18-bpp RGB666
and 24-bpp RGB888 packets and converts the
formatted video data-stream to a FlatLink compatible
LVDS output operating at pixel clocks operating from
25 MHz to 154 MHz, offering a dual-link LVDS,
single-link LVDS, or two Single-Link LVDS interfaces
with four data lanes per link.
The SN65DSI85-Q1 device is well suited for WQXGA
(2560 × 1600) at 60 frames per second (fps), as well
as 3D Graphics at WUXGA and True HD (1920 ×
1080) resolutions at an equivalent 120 fps with up to
24 bits-per-pixel (bpp). Partial line buffering is
implemented to accommodate the data stream
mismatch between the DSI and LVDS interfaces.
The SN65DSI85-Q1 device is implemented in a small
outline 10 mm × 10 mm HTQFP package with a
0.5-mm pitch, and operates across a temperature
range from –40°C to +105°C.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65DSI85-Q1 HTQFP (64)
10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
DA[3:0]P
A_Y0:3N
Application
Processor
With DSI
Output
DA[3:0]N
DACP/N
DB[3:0]P
Dual-Channel
DSI to LVDS
Bridge
A_Y0:3P
A_CLKN/P
SN65SDSI85-Q1
B_Y0:3N
DB[3:0]N
B_Y0:3P
SCL/SDA
B_CLKN/P
TFT LCD Display
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of
development. Subject to change or discontinuance without notice.