SN65CML100_13 Datasheet, PDF (1/19 Pages) Texas Instruments – 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER

SN65CML100
www.ti.com
SLLS547 – NOVEMBER 2002
1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER
FEATURES
• Provides Level Translation From LVDS or
LVPECL to CML, Repeating From CML to CML
• Signaling Rates⁽¹⁾ up to 1.5 Gbps
• CML Compatible Output Directly Drives
Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
• Total Jitter < 70 ps
• Low 100 ps (Max) Part-To-Part Skew
• Wide Common-Mode Receiver Capability
Allows Direct Coupling of Input Signals
• 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
• Propagation Delay Times, 800 ps Maximum
• 3.3-V Supply Operation
• Available in SOIC and MSOP Packages
APPLICATIONS
• Level Translation
• 622-MHz Central Office Clock Distribution
• High-Speed Network Routing
• Wireless Basestations
• Low Jitter Clock Repeater⁽¹⁾
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
FUNCTIONAL DIAGRAM
DESCRIPTION
This high-speed translator/repeater is designed for
signaling rates up to 1.5 Gbps to support various
high-speed network routing applications. The driver
output is compatible with current-mode logic (CML)
levels, and directly drives 50-Ω or 25-Ω loads
connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies.
The capability for direct connection to the loads may
eliminate the need for coupling capacitors. The
receiver input is compatible with LVDS (TIA/EIA-644),
LVPECL, and CML signaling levels. The receiver
tolerates a wide common-mode voltage range, and
may also be directly coupled to the signal source.
The internal data path from input to output is fully
differential for low noise generation and low
pulse-width distortion.
The V_BB pin is an internally generated voltage supply
to allow operation with a single-ended LVPECL input.
For single-ended LVPECL input operation, the
unused differential input is connected to V_BB as a
switching reference voltage. When used, decouple
V_BB with a 0.01-µF capacitor and limit the current
sourcing or sinking to 400 µA. When not used, V_BB
should be left open.
This device is characterized for operation from –40°C
to 85°C.
EYE PATTERN
V_CC ⁸
A2
B
3
4 _VBB
7
Y
6
Z
1.5 Gbps
2²³-1 PRBS
Vertical Scale = 500 mV/div
750 MHz
Horizontal Scale = 200 ps/div
V_CC = 3.3 V, T_A = 25°C, V_ID = 200 mV, V_IC = 1.2 V, V_TT = 3.3 V, R_T = 50 Ω
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–TBD, Texas Instruments Incorporated