SN64BCT657 Datasheet, PDF (1/7 Pages) Texas Instruments – OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS

SN64BCT657
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
AND 3ĆSTATE OUTPUTS
SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994
• State-of-the-Art BiCMOS Design
Significantly Reduces I_CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• High-Impedance State During Power Up
and Power Down
• 3-State B Outputs Sink 64 mA and Source
15 mA
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
DW OR NT PACKAGE
(TOP VIEW)
T/R 1
A1 2
A2 3
A3 4
A4 5
A5 6
V_CC 7
A6 8
A7 ⁹
A8 ¹⁰
ODD/EVEN ¹¹
ERR ¹²
24 OE
23 B1
22 B2
21 B3
20 B4
19 GND
18 GND
17 B5
16 _B6
15 _B7
14 _B8
13 _PARITY
The SN64BCT657 contains eight noninverting buffers with parity generator/checker circuits and control signals.
The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the
A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode).
When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state.
Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity
bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity
generator/checker in the receive mode.
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic
level that maintains the parity sense selected by the level at the ODD/EVEN input. For example, if ODD/EVEN
is low (even parity selected) and there are five high bits on the A bus, then PARITY is set to the logic high level
so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, then ERR
is low, indicating a parity error.
The SN64BCT657 is characterized for operation from − 40°C to 85°C and 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1994, Texas Instruments Incorporated
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