SN64BCT373 Datasheet, PDF (1/4 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

• State-of-the-Art BiCMOS Design
Significantly Reduces I_CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• High-Impedance State During Power Up and
Power Down
• 3-State True Outputs Drive Bus Lines or
Buffer-Memory Address Registers
• Full Parallel Access for Loading
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (N)
SN64BCT373
OCTAL TRANSPARENT DĆTYPE LATCH
WITH 3ĆSTATE OUTPUTS
SCBS065A − JUNE 1990 − REVISED JANUARY 1994
DW OR N PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
description
This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight latches of the SN64BCT373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels
that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive
the bus lines significantly. The high-impedance impedance state and increased drive provide the capability to
drive bus lines without need for interface or pullup components.
The output-enable (OE) does not affect the internal operations of the latches. Old data can be retained or new
data can be entered while the outputs are off.
The outputs are in a high-impedance state during power up and power down while the supply voltage is less
than approximately 3 V.
The SN64BCT373 is characterized for operation from − 40°C to 85°C and 0°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1994, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443