SN54LVTH16835_15 Datasheet, PDF (1/15 Pages) Texas Instruments – 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS

D Members of the Texas Instruments
Widebus ™ Family
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V_CC )
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D I_off and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54LVTH16835, SN74LVTH16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS
WITH 3-STATE OUTPUTS
SCBS713C – MARCH 1998 – REVISED APRIL 1999
SN54LVTH16835 . . . WD PACKAGE
SN74LVTH16835 . . . DGG OR DL PACKAGE
(TOP VIEW)
NC 1
NC 2
Y1 3
GND 4
Y2 5
Y3 6
V_CC 7
Y4 8
Y5 9
Y6 10
GND 11
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
GND 18
Y13 19
Y14 20
Y15 21
V_CC 22
Y16 23
Y17 24
GND 25
Y18 26
OE 27
LE 28
56 GND
55 NC
54 A1
53 GND
52 A2
51 A3
50 V_CC
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 V_CC
34 A16
33 A17
32 GND
31 A18
30 CLK
29 GND
NC – No internal connection
description
The ’LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) V_CC operation, but
with the capability to provide a TTL interface to a 5-V system environment.
Data flow from A to Y is controlled by the output-enable (OE) input. These devices operate in the transparent
mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high
or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock.
When OE is high, the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
1