SN54LVT646_14 Datasheet, PDF (1/18 Pages) Texas Instruments – 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D Support Live Insertion
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and and Thin Shrink Small-Outline
(PW) Packages, Ceramic Chip Carriers
(FK), Ceramic Flat (W) Packages, and
Ceramic (JT) DIPs
description
These bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V_CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
SN54LVT646 . . . JT OR W PACKAGE
SN74LVT646 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
CLKAB 1
SAB 2
DIR 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
A8 11
GND 12
24 V_CC
23 CLKBA
22 SBA
21 OE
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
SN54LVT646 . . . FK PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
A1 5
25 ^OE
A2 6
24 B1
A3 7
23 B2
NC 8
22 NC
A4 9
21 B3
A5 10
20 B4
A6 ¹¹¹² _{13 14 15 16 17 1819} B5
The ’LVT646 consist of bus transceiver circuits,
NC – No internal connection
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high
transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental
bus-management functions that can be performed with the ′LVT646.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1995, Texas Instruments Incorporated
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