SN54LVT2952_14 Datasheet, PDF (1/11 Pages) Texas Instruments – 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SN54LVT2952, SN74LVT2952
3.3ĆV ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3ĆSTATE OUTPUTS
SCBS152E − MAY 1992 − REVISED JULY 1995
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC )
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D Support Live Insertion
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (JT) DIPs
description
These octal bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V_CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
SN54LVT2952 . . . JT PACKAGE
SN74LVT2952 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
B8 1
B7 2
B6 3
B5 4
B4 5
B3 6
B2 7
B1 8
OEAB 9
CLKAB 10
CLKENAB 11
GND 12
24 V_CC
23 A8
22 A7
21 A6
20 A5
19 A4
18 A3
17 A2
16 A1
15 OEBA
14 CLKBA
13 CLKENBA
SN54LVT2952 . . . FK PACKAGE
(TOP VIEW)
B5
B4
B3
NC
B2
B1
OEAB
4 3 2 1 28 27 26
5
25 A6
6
24 A5
7
23 A4
8
22 NC
9
21 A3
10
20 A2
11
19 A1
12 13 14 15 16 17 18
The ’LVT2952 consist of two 8-bit back-to-back
registers that store data flowing in both directions
between two bidirectional buses. Data on the A or
NC − No internal connection
B bus is stored in the registers on the low-to-high
transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input
is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT2952 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT2952 is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74LVT2952 is characterized for operation from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  1995, Texas Instruments Incorporated
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