SN54LVT16245A_08 Datasheet, PDF (1/9 Pages) Texas Instruments – 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D Members of the Texas Instruments
Widebus ™ Family
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC )
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D Support Live Insertion
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes
PCB Layout
D Packaged in Plastic 300-mil Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54LVT16245A, SN74LVT16245A
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS143E – MAY 1992 – REVISED JANUARY 1996
SN54LVT16245A . . . WD PACKAGE
SN74LVT16245A . . . DGG OR DL PACKAGE
(TOP VIEW)
1DIR 1
1B1 2
1B2 3
GND 4
1B3 5
1B4 6
V_CC 7
1B5 8
1B6 9
GND 10
1B7 11
1B8 12
2B1 13
2B2 14
GND 15
2B3 16
2B4 17
V_CC 18
2B5 19
2B6 20
GND 21
2B7 22
2B8 23
2DIR 24
48 1OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 V_CC
41 1A5
40 1A6
39 GND
38 1A7
37 1A8
36 2A1
35 2A2
34 GND
33 2A3
32 2A4
31 V_CC
30 2A5
29 2A6
28 GND
27 2A7
26 2A8
25 2OE
description
The ’LVT16245A are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage (3.3-V) V_CC
operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively
isolated.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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