SN54LV74_10 Datasheet, PDF (1/8 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SN54LV74, SN74LV74
DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS
SCLS189C − FEBRUARY 1993 − REVISED APRIL 1996
D EPIC  (Enhanced-Performance Implanted
CMOS) 2-µ Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These dual positive-edge-triggered D-type flip-
flops are designed for 2.7-V to 5.5-V V_CC
operation.
SN54LV74 . . . J OR W PACKAGE
SN74LV74 . . . D, DP, OR PW PACKAGE
(TOP VIEW)
1CLR ₁
1D 2
1CLK 3
1PRE 4
1Q 5
1Q 6
GND 7
14 ^V_CC
13 2CLR
12 2D
11 2CLK
10 2PRE
9 2Q
8 2Q
SN54LV74 . . . FK PACKAGE
(TOP VIEW)
1CLK
NC
1PRE
NC
1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2D
NC
2CLK
NC
2PRE
A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs regardless of the
levels of the other inputs. When PRE and CLR are
NC − No internal connection
inactive (high), data at the data (D) inputs meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed
without affecting the levels at the outputs.
The SN74LV74 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV74 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV74 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  1996, Texas Instruments Incorporated
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