SN54LV74A_15 Datasheet, PDF (1/31 Pages) Texas Instruments – Dual Positive-Edge-Triggered D-Type Flip-Flops

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SN54LV74A, SN74LV74A
SCLS381M – AUGUST 1997 – REVISED MARCH 2015
SNx4LV74A Dual Positive-Edge-Triggered D-Type Flip-Flops
1 Features
•1 2-V to 5.5-V V_CC Operation
• Maximum t_pd of 8.5 ns at 5 V
• Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
> 2.3 V at V_CC = 3.3 V, T_A = 25°C
• Support Mixed-Mode Voltage Operation on
All Ports
• I_off Supports Partial-Power-Down
Mode Operation
• Latch-up Performance Exceeds 250 mA
Per JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 500-V Charged-Device Model (C101)
2 Applications
• Programmable Logic Controller (PLC)
• DCS and PAC: Analog Input Module
• AV Receiver
• Server PSU
• STB, DVR, and Streaming Media (Withdraw)
• Server Motherboard
3 Description
These dual positive-edge-triggered D-type flip-flops
are designed for 2-V to 5.5-V V_CC operation.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
VQFN (14)
3.50 mm × 3.50 mm
SOIC (14)
8.65 mm × 3.91 mm
SN74LV74A
SOP (14)
10.30 mm × 5.30 mm
SSOP (14)
6.20 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Flip-Flop
(Positive Logic)
PRE
CLK
C
C
C
Q
TG
C
C
D
TG
TG
C
C
TG
Q
C
C
C
CLR
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.