SN54LV574_16 Datasheet, PDF (1/13 Pages) Texas Instruments – OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54LV574, SN74LV574
OCTAL EDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS
WITH 3ĆSTATE OUTPUTS
SCLS199B − MARCH 1993 − REVISED APRIL 1996
D EPIC  (Enhanced-Performance Implanted
CMOS) 2-µ Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
SN54LV574 . . . J OR W PACKAGE
SN74LV574 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
GND 10
20 V_CC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 CLK
SN54LV574 . . . FK PACKAGE
(TOP VIEW)
description
These octal edge-triggered D-type flip-flops are
designed for 2.7-V to 5.5-V V_CC operation.
The ’LV574 feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
3D
3 2 1 20 19
4
18
2Q
4D 5
17 3Q
5D 6
16 4Q
6D 7
15 5Q
7D 8
14 6Q
9 10 11 12 13
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data
(D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN74LV574 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV574 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV574 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  1996, Texas Instruments Incorporated
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