SN54LV138 Datasheet, PDF (1/8 Pages) Texas Instruments – 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SN54LV138, SN74LV138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS190D – FEBRUARY 1993 – REVISED JULY 1996
D EPIC ™ (Enhanced-Performance Implanted
CMOS) 2-µ Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC, T_A = 25°C
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These 3-line to 8-line decoders/demultiplexers
are designed for 2.7-V to 5.5-V V_CC operation.
The ’LV138 are designed for high-performance
memory-decoding or data-routing applications
requiring very short propagation delay times. In
high-performance memory systems, this decoder
can be used to minimize the effects of system
decoding. When employed with high-speed
utilizing a fast enable circuit, the delay times of this
decoder and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoder is negligible.
SN54LV138 . . . J OR W PACKAGE
SN74LV138 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
A₁
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
GND 8
16 ^V_CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
SN54LV138 . . . FK PACKAGE
(TOP VIEW)
C
3 2 1 20 19
4
18
Y1
G2A 5
17 Y2
NC 6
16 NC
G2B 7
15 Y3
G1 8
14 Y4
9 10 11 12 13
NC – No internal connection
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
The SN74LV138 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV138 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV138 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1996, Texas Instruments Incorporated
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