SN54LS224A Datasheet, PDF (1/13 Pages) Texas Instruments – 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS

SN54LS224A, SN74LS224A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
D Independent Synchronous Inputs and
Outputs
D 16 Words by 4 Bits Each
D 3-State Outputs Drive Bus Lines Directly
D Data Rates up to 10 MHz
D Fall-Through Time 50 ns Typical
D Data Terminals Arranged for Printed Circuit
Board Layout
D Expandable, Using External Gating
D Packaged in Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Chip
Carriers (FK)
description
SN54LS224A . . . J PACKAGE
SN74LS224A . . . N PACKAGE
(TOP VIEW)
OE ¹
IR ²
LDCK ³
D0 4
D1 5
D2 6
D3 7
GND 8
16 V_CC
15 UNCK
14 OR
13 Q0
12 Q1
11 Q2
10 Q3
9 CLR
SN54LS224A . . . FK PACKAGE
(TOP VIEW)
The SN54LS224A and SN74LS224A 64-bit,
low-power Schottky memories are organized as
16 words by 4 bits each. They can be expanded
in multiples of 15m + 1 words or 4n bits, or both
(where n is the number of packages in the vertical
array and m is the number of packages in the
horizontal array); however, some external gating
is required. For longer words, the input-ready (IR)
signals of the first-rank packages and
output-ready (OR) signals of the last-rank
packages must be ANDed for proper
synchronization.
3 2 1 20 19
LDCK 4
18 OR
D0 5
17 Q0
NC ⁶
16 _NC
D1 ⁷
15 _Q1
D2 ⁸
14 _Q2
9 10 11 12 13
A first-in, first-out (FIFO) memory is a storage
device that allows data to be written to and read
from its array at independent data rates. These
FIFOs are designed to process data at rates up to
10 MHz in a bit-parallel format, word by word.
NC – No internal connection
The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of
LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of
UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked
out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory
is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions.
IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty
and UNCK is high.
A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low
to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting, with respect to
the data inputs, and are at high impedance when the output-enable (OE) input is low. OE does not affect the
IR and OR outputs.
The SN74LS224A is characterized for operation from 0°C to 70°C. The SN54LS224A is characterized over the
full military temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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