SN54HCT126_08 Datasheet, PDF (1/5 Pages) Texas Instruments – QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

D High-Current 3-State Outputs Drive Bus
Lines or Buffer Memory Address Registers
D Inputs Are TTL-Voltage Compatible
D Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These bus buffers feature independent line
drivers with 3-state outputs. Each output is
disabled when the associated OE is low.
The SN54HCT126 is characterized for operation
over the full military temperature range of −55°C
to 125°C. The SN74HCT126 is characterized for
operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
H = high level, L = low level,
X = irrelevant
SN54HCT126, SN74HCT126
QUADRUPLE BUS BUFFER GATES
WITH 3ĆSTATE OUTPUTS
SCLS070A − NOVEMBER 1988 − REVISED NOVEMBER 1990
SN54HCT126 . . . J PACKAGE
SN74HCT126 . . . D OR N PACKAGE
(TOP VIEW)
1OE ₁
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 ^V_CC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
SN54HCT126 . . . FK PACKAGE
(TOP VIEW)
1Y
NC
2OE
NC
2A
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3OE
NC − No internal connection
logic symbol^†
logic diagram, each buffer (positive logic)
1
1OE
EN
3
OE
2
1Y
1A
4
2OE
6
A
Y
5
2Y
2A
10
3OE
9
8
3Y
3A
13
4OE
11
12
4Y
4A
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and}
IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  1990, Texas Instruments Incorporated
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