SN54HC74_15 Datasheet, PDF (1/15 Pages) Texas Instruments – Dual D-Type Positive-Edge-Triggered Flip-Flops

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SN54HC74, SN74HC74
SCLS094E – DECEMBER 1982 – REVISED DECEMBER 2015
SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset
1 Features
•1 Wide Operating Voltage Range: 2 V to 6 V
• Outputs Can Drive Up To 10 LSTTL Loads
• Low Power Consumption, 40-µA Maximum I_CC
• Typical t_pd = 15 ns
• ±4-mA Output Drive at 5 V
• Very Low Input Current of 1 µA
2 Applications
• Ultrasound System
• Fans
• Lab Instrumentation
• Vacuum Cleaners
• Video Communications System
• IP Phone: Wired
3 Description
The SNx4HC74 devices contain two independent D-
type positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or resets
the outputs, regardless of the levels of the other
inputs. When PRE and CLR are inactive (high), data
at the data (D) input meeting the setup time
requirements are transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of CLK. Following the hold-
time interval, data at the D input can be changed
without affecting the levels at the outputs.
Device Information⁽¹⁾
PART NUMBER PACKAGE
BODY SIZE (NOM)
SN74HC74N
PDIP (14)
19.30 mm x 6.40 mm
SN74HC74NS SO (14)
10.20 mm x 5.30 mm
SN74HC74D
SOIC (14)
8.70 mm x 3.90 mm
SN74HC74DB SSOP (14) 6.50 mm x 5.30 mm
SN74HC74PW TSSOP (14) 5.00 mm x 4.40 mm
SNJ54HC74J
CDIP (14)
21.30 mm x 7.60 mm
SNJ54HC74W CFP (14)
9.20 mm x 6.29 mm
SNJ54HC74FK LCCC (20) 8.90 mm x 8.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
PRE
C
CLK
C
Q
C
TG
C
C
C
C
D
TG
TG
TG
CLR
C
C
Q
C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.