SN54HC563_16 Datasheet, PDF (1/15 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

D Wide Operating Voltage Range of 2 V to 6 V
D High-Current 3-State Outputs Drive Bus
Lines Directly or Up To 15 LSTTL Loads
D Low Power Consumption, 80-µA Max I_CC
SN54HC563 . . . J OR W PACKAGE
SN74HC563 . . . DW OR N PACKAGE
(TOP VIEW)
SN54HC563, SN74HC563
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS145C – DECEMBER 1982 – REVISED MARCH 2003
D Typical t_pd = 21 ns
D ±6-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Bus-Structured Pinout
SN54HC563 . . . FK PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D ⁵
5D 6
6D ⁷
7D ⁸
8D ⁹
GND ¹⁰
20 V_CC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
3D
3 2 1 20 19
4
18
2Q
4D ₅
17 ^3Q
5D 6
16 4Q
6D 7
15 5Q
7D 8
14 6Q
9 10 11 12 13
description/ordering information
These 8-bit transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When
LE is taken low, the outputs are latched at the inverses of the levels set up at the D inputs.
A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines
without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74HC563N
SN74HC563N
–40°C to 85°C
SOIC – DW
Tube
Tape and reel
SN74HC563DW
SN74HC563DWR
HC563
CDIP – J
Tube
SNJ54HC563J
SNJ54HC563J
–55°C to 125°C CFP – W
Tube
SNJ54HC563W
SNJ54HC563W
LCCC – FK
Tube
SNJ54HC563FK
SNJ54HC563FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  2003, Texas Instruments Incorporated
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