SN54HC191-DIE Datasheet, PDF (1/6 Pages) Texas Instruments – 4-Bit Synchronous Up/Down Binary Counter

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SN54HC191-DIE
SCLS748 – MARCH 2014
SN54HC191-DIE 4-Bit Synchronous Up/Down Binary Counter
1 Features
• Wide Operating Voltage Range
• Low Power Consumption
• Low Input Current
• Single Down/Up Count-Control Line
• Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
• Fully Synchronous in Count Modes
• Asynchronously Presettable With Load Control
2 Description
The SN54HC191-DIE is a 4-bit synchronous,
reversible, up/down binary counter. Synchronous
counting operation is provided by having all flip-flops
clocked simultaneously so that the outputs change
coincident with each other when instructed by the
steering logic. This mode of operation eliminates the
output counting spikes normally associated with
asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a
low- to high-level transition of the clock (CLK) input if
the count-enable (CTEN) input is low. A high at
CTEN inhibits counting. The direction of the count is
determined by the level of the down/up (D/U) input.
When D/U is low, the counter counts up, and when
D/U is high, it counts down.
1
These counters feature a fully independent clock
circuit. Change at the control (CTEN and D/U) inputs
that modifies the operating mode have no effect on
the contents of the counter until clocking occurs. The
function of the counter is dictated solely by the
condition meeting the stable setup and hold times.
These counters are fully programmable; that is, each
of the outputs can be preset to either level by placing
a low on the load (LOAD) input and entering the
desired data at the data inputs. The output changes
to agree with the data inputs independently of the
level of CLK. This feature allows the counters to be
used as modulo-N dividers simply by modifying the
count length with the preset inputs.
Two outputs are available to perform the cascading
function: ripple clock (RCO) and maximum/minimum
(MAX/MIN) count. MAX/MIN produces a high-level
output pulse with a duration approximately equal to
one complete cycle of the clock while the count is
zero (all outputs low) counting down, or maximum (9
or 15) counting up. RCO produces a low-level output
pulse under those same conditions, but only while
CLK is low. The counters can be cascaded easily by
feeding RCO to CTEN of the succeeding counter if
parallel clocking is used, or to CLK if parallel enabling
is used. MAX/MIN can be used to accomplish look
ahead for high-speed operation.
PRODUCT
SN54HC191
PACKAGE
DESIGNATOR
TD
Ordering Information⁽¹⁾
PACKAGE
ORDERABLE PART NUMBER
Bare die in waffle pack⁽²⁾
SN54HC191TDE1
SN54HC191TDE2
PACKAGE QUANTITY
154
10
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Processing is per the Texas Instruments space production baseline and is in compliance with the Texas Instruments Quality Control
System in effect at the time of manufacture. Electrical screening consists of DC parametric and functional testing at room temperature
only. Unless otherwise specified by Texas Instruments AC performance and performance over temperature is not warranted. Visual
Inspection is performed in accordance with MIL-STD-883 Test Method 2010 Condition B at 75X minimum.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.