SN54HC165_15 Datasheet, PDF (1/31 Pages) Texas Instruments – 8-Bit Parallel-Load Shift Registers

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SN54HC165, SN74HC165
SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015
SNx4HC165 8-Bit Parallel-Load Shift Registers
1 Features
•1 Wide Operating Voltage Range of 2 V to 6 V
• Outputs Can Drive Up to 10 LSTTL Loads
• Low Power Consumption, 80-µA Maximum I_CC
• Typical t_pd = 13 ns
• ±4-mA Output Drive at 5 V
• Low Input Current of 1 µA Maximum
• Complementary Outputs
• Direct Overriding Load (Data) Inputs
• Gated Clock Inputs
• Parallel-to-Serial Data Conversion
• On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
2 Applications
• Programable Logic Controllers
• Appliances
• Video Display Systems
• Output Expander
• Keyboards
3 Description
The SNx4HC165 devices are 8-bit parallel-load shift
registers that, when clocked, shift the data toward a
serial (Q_H) output. Parallel-in access to each stage is
provided by eight individual direct data (A−H) inputs
that are enabled by a low level at the shift/load
(SH/LD) input. The SNx4HC165 devices also feature
a clock-inhibit (CLK INH) function and a
complementary serial (Q_H) output.
Clocking is accomplished by a low-to-high transition
of the clock (CLK) input while SH/LD is held high and
CLK INH is held low. The functions of CLK and CLK
INH are interchangeable. Because a low CLK and a
low-to-high transition of CLK INH also accomplish
clocking, CLK INH must be changed to the high level
only while CLK is high. Parallel loading is inhibited
when SH/LD is held high. While SH/LD is low, the
parallel inputs to the register are enabled
independently of the levels of the CLK, CLK INH, or
serial (SER) inputs.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HC165D
SOIC (16)
10.00 mm × 6.20 mm
SN74HC165DB
SSOP (16)
8.20 mm × 6.50 mm
SN74HC165N
PDIP (16)
6.60 mm × 18.92 mm
SN74HC165NS
SO (16)
8.20 mm × 9.90 mm
SN74HC165PW
TSSOP (16)
6.60 mm × 5.10 mm
SN54HC165FK
LCCC (20)
9.09 mm × 9.09 mm
SN54HC165J
CDIP (16)
21.34 mm × 7.52 mm
SN54HC165W
CFP (16)
9.40 mm × 7.75 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SH/LD ¹
15
CLK INH
2
CLK
10
SER
Logic Diagram Positive Logic
A
B
C
D
E
F
G
H
11
12
13
14
3
4
5
6
9
Q_H
S
S
S
S
S
S
S
S
C1
C1
C1
C1
C1
C1
C1
C1
1D
1D
1D
1D
1D
1D
1D
1D
R
R
R
R
R
R
R
R
Pin numbers shown are for theD, DB, J, N, NS, PW, and W packages.
7
Q_H
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.