SN54CDC586_07 Datasheet, PDF (1/11 Pages) Texas Instruments – 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUPUTS

SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311A – FEBRUARY 1997 – REVISED JULY 2002
D Low Output Skew for Clock-Distribution
and Clock-Generation Applications
D Operates at 3.3-V V_CC
D Distributes One Clock Input to 12 Outputs
D Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency
D No External RC Network Required
D External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
D Application for Synchronous DRAM,
High-Speed Microprocessor
D TTL-Compatible Inputs and Outputs
D Outputs Drive Parallel 50-Ω Terminated
Transmission Lines
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
D Distributed V_CC and Ground Pins Reduce
Switching Noise
D Packaged in 56-Pin Ceramic Flat Package
description
The SN54CDC586 is a high-performance,
low-skew, low-jitter clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the clock output signals to
the clock input (CLKIN) signal. It is specifically
designed for use with popular microprocessors
operating at speeds from 50 MHz to 100 MHz, or
down to 25 MHz on outputs configured as
half-frequency outputs. The SN54CDC586
W ^{operates at 3.3-V VCC and is designed to drive a}
properly terminated 50- transmission line.
WD PACKAGE
(TOP VIEW)
NC 1
AV_CC 2
AGND 3
FBIN 4
AGND 5
SEL0 6
SEL1 ⁷
GND ⁸
GND ⁹
1Y1 ¹⁰
V_CC ¹¹
GND ¹²
1Y2 ¹³
V_CC ¹⁴
GND ¹⁵
1Y3 ¹⁶
V_CC ¹⁷
GND ¹⁸
GND ¹⁹
2Y1 ²⁰
V_CC ²¹
GND ²²
2Y2 ²³
V_CC ²⁴
GND ²⁵
2Y3 ²⁶
V_CC ²⁷
NC ²⁸
56 NC
55 CLKIN
54 NC
53 AV_CC
52 OE
51 TEST
50 _CLR
49 _VCC
48 _4Y3
47 _GND
46 _VCC
45 _4Y2
44 _GND
43 _VCC
42 _4Y1
41 _GND
40 _GND
39 _VCC
38 _3Y3
37 _GND
36 _VCC
35 _3Y2
34 _GND
33 _VCC
32 _3Y1
31 _GND
30 _GND
29 _NC
NC – No internal connection
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to CLKIN. One of
the 12 output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input
and the outputs. The output used as the feedback pin is synchronized to the same frequency as the CLKIN input.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs
(SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN
frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output-signal duty cycles are
adjusted to 50%, independent of the duty cycle at CLKIN.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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