SN54AS866_08 Datasheet, PDF (1/7 Pages) Texas Instruments – 8-BIT MAGNITUDE COMPARATORS

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SN54AS866, SN74AS866A
8ĆBIT MAGNITUDE COMPARATORS
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SDAS183A − DECEMBER 1982 − REVISED JUNE 1990
• Package Options Include Plastic Small
Outline Packages, Both Plastic and Ceramic
Chip Carriers, and Standard Plastic and
Ceramic DIPs
• Input and Output Latches with Active-High
Enables
• Fast Compare to Zero
• Arithmetic and Logical Comparison
• Open-Collector P = Q Output
description
These Advanced Schottky devices are capable of
performing high-speed arithmetic or logical
comparisons on two 8-bit binary or two’s
complement words. Three fully decoded
decisions about words P and Q are externally
available at the outputs. These devices are fully
expandable to any word length by connecting the
totem pole P>Q and P<Q outputs of each stage to
the P>Q and P<Q inputs of the next higher-order
stage. The cascading paths are implemented with
only a two-gate-level delay to reduce overall
comparison times for long words. The open-
collector P=Q output may be wire-ANDed
together.
Both input words P and Q plus all three outputs
(P>Q, P<Q, and P = Q) are equipped with latches
to provide the designer with temporary data
storage for avoiding race conditions. The enable
circuitry is implemented with minimal delay times
to enhance performance when the devices are
cascaded for longer word lengths. Each latch is
transparent when the appropriate latch enable,
PLE, QLE, or OLE is high.
SN54AS866 . . . JD PACKAGE
SN74AS866A . . . N PACKAGE
(TOP VIEW)
QLE ₁
L/A 2
p < Qin 3
P > Qin 4
Q7 5
Q6 6
Q5 7
Q4 8
Q3 9
Q2 10
Q1 ¹¹
Q0 ¹²
P = Qout ¹³
GND ¹⁴
28 ^V_CC
27 CLRQ
26 PLE
25 P7
24 P6
23 P5
22 P4
21 P3
20 P2
19 P1
18 _P0
17 _{P < Qout}
16 _{P > Qout}
15 _OLE
SN54AS866 . . . FK PACKAGE
SN74AS866A . . . FN PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
Q7 ⁵
25 P7
Q6 ⁶
24 P6
Q5 ⁷
23 P5
Q4 ⁸
22 P4
Q3 ⁹
21 P3
Q2 ¹⁰
20 P2
Q1 ¹¹
19 P1
12 13 14 15 16 17 18
The enable inputs PLE and QLE and data inputs
P and Q utilize pnp input transistors to reduce the
low-level input current requirement to typically
−0.25 mA, which minimizes loading effects.
The Q register may be cleared to zero for a fast comparison of the P word to zero.
The SN54AS866 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74AS866A is characterized for operation from 0°C to 70°C.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  1990, Texas Instruments Incorporated
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