SN54ALVTH16821_08 Datasheet, PDF (1/17 Pages) Texas Instruments – 2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus ™ Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V_CC )
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D High-Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V_CC)
D Power Off Disables Outputs, Permitting
Live Insertion
D High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
D Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
D Auto3-State Eliminates Bus Current
Loading When Output Exceeds V_CC + 0.5 V
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
D Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16821 . . . WD PACKAGE
SN74ALVTH16821 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
V_CC 7
1Q5 8
1Q6 9
1Q7 10
GND 11
1Q8 12
1Q9 13
1Q10 14
2Q1 15
2Q2 16
2Q3 17
GND 18
2Q4 19
2Q5 20
2Q6 21
V_CC 22
2Q7 23
2Q8 24
GND 25
2Q9 26
2Q10 27
2OE 28
56 1CLK
55 1D1
54 1D2
53 GND
52 1D3
51 1D4
50 V_CC
49 1D5
48 1D6
47 1D7
46 GND
45 1D8
44 1D9
43 1D10
42 2D1
41 2D2
40 2D3
39 GND
38 2D4
37 2D5
36 2D6
35 V_CC
34 2D7
33 2D8
32 GND
31 2D9
30 2D10
29 2CLK
description
The ’ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V
V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered
D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the
D inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1999, Texas Instruments Incorporated
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