SN54ALS561A_11 Datasheet, PDF (1/13 Pages) Texas Instruments – SYNCHRONOUS 4-BIT COUNTERS

• Carry Output for n-Bit Cascading
• Buffer-Type Outputs Drive Bus Lines
Directly
• Choice of Asynchronous or Synchronous
Clearing and Loading
• Internal Look-Ahead Circuitry for Fast
Cascading
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
SN54ALS561A . . . J PACKAGE
SN74ALS561A . . . DW OR N PACKAGE
(TOP VIEW)
ALOAD 1
CLK 2
A3
B4
C5
D6
ENP 7
ACLR 8
SCLR 9
GND 10
20 V_CC
19 RCO
18 CCO
17 OE
16 Q_A
15 Q_B
14 Q_C
13 Q_D
12 ENT
11 SLOAD
These binary counters are programmable and
offer synchronous and asynchronous clearing as
well as synchronous and asynchronous loading.
All synchronous functions are executed on the
positive-going edge of the clock.
SN54ALS561A . . . FK PACKAGE
(TOP VIEW)
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR) or
synchronous clear (SCLR). ACLR (direct clear)
overrides all other functions of the device, while
SCLR overrides only the other synchronous
functions. Data is loaded from the A, B, C, and D
inputs by applying a low level to asynchronous
load (ALOAD) or by the combination of a low level
at synchronous load (SLOAD) and a
positive-going clock transition. The counting
function is enabled only when enable P (ENP),
enable T (ENT), ACLR, ALOAD, SCLR, and
SLOAD are all high.
B
C
D
ENP
ACLR
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
CCO
OE
Q_A
Q_B
Q_C
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output
(RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces
a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is
enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated
with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter
to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because
CCO does not become active until the clock returns to the low level.
The SN54ALS561A is characterized for operation over the full military temperature range of – 55°C to 125°C.
The SN74ALS561A is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1995, Texas Instruments Incorporated
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