SN54ALS114A Datasheet, PDF (1/4 Pages) Texas Instruments – DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR AND COMMON CLOCK

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SN54ALS114A, SN74ALS114A
DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH PRESET,COMMON CLEAR,AND COMMON CLOCK
SDAS201 − D2661, DECEMBER 1982 − REVISED MAY 1986
• Fully Buffered to Offer Maximum isolation
from External Disturbance
• Package Options include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
• Typical Maximum Clock Frequency
30 MHz
• Typical Power Dissipation per Flip-Flop
6 mW
• Dependable Texas Instruments Quality and
Reliability
description
SN54ALS114A . . . J PACKAGE
SN74ALS114A . . . D OR N PACKAGE
(TOP VIEW)
CLR 1
1K 2
1J 3
1PRE 4
1Q 5
1Q 6
GND 7
14 V_CC
13 CLK
12 ^2K
11 ^2J
10 ^2PRE
9 ^2Q
8 ^2Q
SN54ALS114A . . . FK PACKAGE
(TOP VIEW)
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets or resets the
outputs regardless of the levels of the other inputs.
When Preset and Clear are inactive (high), data at
the J and K inputs meeting the setup time
requirements are transferred to the outputs on the
negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the fall time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by tying J and K high.
The SN54ALS114A is characterized for operation
over the full military temperature range of − 55°C
to 125°C. The SN74ALS114A is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H†
H†
H
H
↓
L
L
Q0
Q0
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
TOGGLE
H
H
H
X
X
Q0
Q0
† _{The output levels in this configuration are not guaranteed to}
meet the minimum levels for VOH if the lows at Preset and
Clear are near VIL maximum. Furthermore, this configuration
is nonstable; that is, it will not persist when either Preset or
Clear returns to its inactive (high) level.
1J
NC
1PRE
NC
1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2K
NC
2J
NC
2PRE
NC−No internal connection
logic symbol^‡
1
CLR
13
CLK
4
1PRE
3
1J
2
1K
10
2PRE
11
2J
12
2K
R
C1
S
1J
1K
5
1Q
6
1Q
9
2Q
8
2Q
‡ _{This symbol is in accordance with ANSI/IEEE Std 911-1984 and}
IEC Publication 617-12.
Pin numbers are for D, J, and N packages.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
Copyright  1986, Texas Instruments Incorporated
5BASIC
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