SN54ALS109A_15 Datasheet, PDF (1/19 Pages) Texas Instruments – DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A
DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH CLEAR AND PRESET
SDAS198B − APRIL 1982 − REVISED AUGUST 1995
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
TYPE
′ALS109A
′AS109A
TYPICAL MAXIMUM
CLOCK
FREQUENCY
(MHz)
50
129
TYPICAL POWER
DISSIPATION
PER FLIP-FLOP
(mW)
6
29
description
SN54ALS109A, SN54AS109A . . . J PACKAGE
SN74ALS109A, SN74AS109A . . . D OR N PACKAGE
(TOP VIEW)
1CLR 1
1J 2
1K 3
1CLK 4
1PRE 5
1Q 6
1Q 7
GND 8
16 V_CC
15 2CLR
14 2J
13 2K
12 2CLK
11 2PRE
10 2Q
9 2Q
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the rise time of
the clock pulse. Following the hold-time interval,
data at the J and K inputs can be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by
grounding K and tying J high. They also can
perform as D-type flip-flops if J and K are tied
together.
SN54ALS109A, SN54AS109A . . . FK PACKAGE
(TOP VIEW)
1K
1CLK
NC
1PRE
1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2J
2K
NC
2CLK
2PRE
NC − No internal connection
The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range
of −55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H†
H†
H
H
↑
L
L
L
H
H
H
↑
H
L
Toggle
H
H
↑
L
H
Q0 Q0
H
H
↑
H
H
H
L
H
H
L
X
X
Q0 Q0
† _{The output levels in this configuration are not specified to}
meet the minimum levels for VOH if the lows at PRE and
CLR are near VIL maximum. Furthermore, this
configuration is nonstable; that is, it does not persist when
either PRE or CLR returns to its inactive (high) level.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1995, Texas Instruments Incorporated
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