SN54ACT533_14 Datasheet, PDF (1/10 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54ACT533, SN74ACT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS553C – NOVEMBER 1995 – REVISED OCTOBER 2002
D 4.5-V to 5.5-V V_CC Operation
D Inputs Accept Voltages to 5.5 V
D Max t_pd of 11 ns at 5 V
D Inputs Are TTL-Voltage Compatible
D 3-State Inverting Outputs Drive Bus Lines
Directly
description/ordering information
The ’ACT533 devices are octal transparent
D-type latches with 3-state outputs. When the
latch-enable (LE) input is high, the Q outputs
follow the complements of the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the inverted levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect the internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
SN54ACT533 . . . J OR W PACKAGE
SN74ACT533 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
SN54ACT533 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
2D 4
18 8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 _6Q
4D ⁸
14 _6D
9 10 11 12 13
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74ACT533N
SN74ACT533N
–40°C to 85°C
SOIC – DW
SOP – NS
Tube
Tape and reel
Tape and reel
SN74ACT533DW
SN74ACT533DWR
SN74ACT533NSR
ACT533
ACT533
SSOP – DB
Tape and reel SN74ACT533DBR
AD533
TSSOP – PW
Tape and reel SN74ACT533PWR
AD533
CDIP – J
–55°C to 125°C CFP – W
Tube
Tube
SNJ54ACT533J
SNJ54ACT533W
SNJ54ACT533J
SNJ54ACT533W
LCCC – FK
Tube
SNJ54ACT533K
SNJ54ACT533FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  2002, Texas Instruments Incorporated
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