SN54ABTH162260_08 Datasheet, PDF (1/12 Pages) Texas Instruments – 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS

SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MAY 1997
D Members of the Texas Instruments
Widebus™ Family
D B-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical V_OLP (Output Ground Bounce)
< 1 V at V_CC = 5 V, T_A = 25°C
D High-Impedance State During Power Up
and Power Down
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
SN54ABTH162260 . . . WD PACKAGE
SN74ABTH162260 . . . DL PACKAGE
(TOP VIEW)
OEA 1
LE1B 2
2B3 3
GND 4
2B2 5
2B1 6
V_CC 7
A1 8
A2 9
A3 10
GND 11
A4 12
A5 13
A6 14
A7 15
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
V_CC 22
1B1 23
1B2 24
GND 25
1B3 26
LE2B 27
SEL 28
56 OE2B
55 LEA2B
54 2B4
53 GND
52 2B5
51 2B6
50 V_CC
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
35 V_CC
34 1B6
33 1B5
32 GND
31 1B4
30 LEA1B
29 OE1B
The ’ABTH162260 are 12-bit to 24-bit multiplexed D-type latches used in applications where two separate data
paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include
multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface
applications. These devices are also useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The
output-enable (OE1B, OE2B, and OEA) inputs control the bus-transceiver functions. The OE1B and OE2B
control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The B-port outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce
overshoot and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1997, Texas Instruments Incorporated
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