SN54ABT823_15 Datasheet, PDF (1/18 Pages) Texas Instruments – 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54ABT823, SN74ABT823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS158E – JANUARY 1991 – REVISED MAY 1997
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical V_OLP (Output Ground Bounce) < 1 V
at V_CC = 5 V, T_A = 25°C
D High-Impedance State During Power Up
and Power Down
D High-Drive Outputs (–32-mA I_OH, 64-mA I_OL)
D Buffered Control Inputs to Reduce
dc Loading Effects
D Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic Chip
Carriers (FK) and Flatpacks (W), and
Standard Plastic (NT) and Ceramic (JT)
DIPs
SN54ABT823 . . . JT OR W PACKAGE
SN74ABT823 . . . DB, DW, OR NT PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
9D 10
CLR 11
GND 12
24 V_CC
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 CLKEN
13 CLK
SN54ABT823 . . . FK PACKAGE
(TOP VIEW)
description
These 9-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
4 3 2 1 28 27 26
3D 5
25 ^3Q
4D 6
24 ^4Q
5D 7
23 ^5Q
NC 8
22 ^NC
6D 9
21 ^6Q
7D 10
20 ^7Q
8D 11
19 ^8Q
12 13 14 15 16 17 18
With the clock-enable (CLKEN) input low, the nine
D-type edge-triggered flip-flops enter data on the
low-to-high transitions of the clock. Taking CLKEN
high disables the clock buffer, thus latching the
outputs. Taking the clear (CLR) input low causes
the nine Q outputs to go low, independently of the
clock.
NC – No internal connection
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V_CC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT823 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT823 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
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