SN54ABT657A_09 Datasheet, PDF (1/13 Pages) Texas Instruments – OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical V_OLP (Output Ground Bounce) < 1 V
at V_CC = 5 V, T_A = 25°C
D High-Impedance State During Power Up
and Power Down
D Flow-Through Architecture Optimizes PCB
Layout
D High-Drive Outputs (–32-mA I_OH, 64-mA I_OL)
D Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
SN54ABT657A . . . JT PACKAGE
SN74ABT657A . . . DW OR NT PACKAGE
(TOP VIEW)
T/R 1
A1 2
A2 3
A3 4
A4 5
A5 6
V_CC 7
A6 8
A7 9
A8 10
ODD/EVEN 11
ERR 12
24 OE
23 B1
22 B2
21 B3
20 B4
19 GND
18 GND
17 B5
16 B6
15 B7
14 B8
13 PARITY
SN54ABT657A . . . FK PACKAGE
(TOP VIEW)
description
The 'ABT657A transceivers have eight
noninverting buffers with parity-generator/
checker circuits and control signals. The
transmit/receive (T/R) input determines the
direction of data flow. When T/R is high, data flows
from the A port to the B port (transmit mode); when
T/R is low, data flows from the B port to the A port
(receive mode). When the output-enable (OE)
input is high, both the A and B ports are in the
high-impedance state.
4 3 2 1 28 27 26
ODD/EVEN 5
25 A3
ERR 6
24 A2
PARITY 7
23 _A1
NC 8
22 _NC
B8 9
21 _T/R
B7 10
20 _OE
B6 11
19 _B1
12 13 14 15 16 17 18
Odd or even parity is selected by a logic high or
low level on the ODD/EVEN input. PARITY carries
the parity-bit value; it is an output from the parity
generator/checker in the transmit mode and an
input to the parity generator/checker in the receive
mode.
NC – No internal connection
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic
level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low
(even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an
even number of the nine total bits (eight A-bus bits plus parity bit) are high.
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is
low, indicating a parity error.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright © 1997, Texas Instruments Incorporated
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