SN100KT5541 Datasheet, PDF (1/8 Pages) Texas Instruments – OCTAL ECL-TO-TTL TRANSLATOR WITH 3-STATE OUTPUTS

• 100K Compatible
• ECL and TTL Control Inputs
• Noninverting Outputs
• Flow-Through Architecture Optimizes PCB
Layout
• Center Pin V_CC, V_EE, and GND
Configurations Minimize High-Speed
Switching Noise
• Package Options Include “Small Outline”
Packages and Standard Plastic 300-mil
DIPs
description
This octal ECL-to-TTL translator is designed to
provide a efficient translation between a 100K
ECL signal environment to a TTL signal
environment. This device is designed specifically
to
improve
the performance and density of ECL-to-TTL
CPU/bus-oriented functions such as
memory-address drivers, clock drivers, and
bus-oriented receivers and transmitters.
Two output-enable pins, OE1 and OE2 are
provided. These control inputs are ANDed
together with OE1 being ECL compatible and OE2
being TTL compatible. This offers the choice of
controlling the outputs of the device from either a
TTL or ECL signal environment.
The SN100KT5541 is characterized for operation
from 0°C to 85°C.
FUNCTION TABLE
OUTPUT
ENABLE
OE1 OE2
X
H
H
X
L
L
L
L
DATA
INPUT
A
X
X
L
H
OUTPUT
(TTL)
Y
Z
Z
L
H
SN100KT5541
OCTAL ECLĆTOĆTTL TRANSLATOR
WITH 3ĆSTATE OUTPUTS
SDZS004A − NOVEMBER 1989 − REVISED MAY 1990
DW OR NT PACKAGE
(T0P VIEW)
Y1 ₁
Y2 ₂
Y3 ₃
Y4 ₄
V_{CC 5}
GND ₆
GND 7
GND 8
Y5 9
Y6 10
Y7 11
Y8 12
24 ^A1
23 ^A2
22 ^A3
21 ^A4
20 ^{OE2 (TTL)}
19 ^V_EE
18 GND
17 OE1 (ECL)
16 A5
15 A6
14 A7
13 A8
logic symbol^†
OE1 ¹⁷
OE2 ²⁰
ECL/TTL &
EN
A1 ²⁴
A2 ²³
A3 ²²
A4 ²¹
16
A5
15
A6
14
A7
A8 ¹³
ECL/TTL
1 _Y1
2 _Y2
3 _Y3
4 _Y4
9
Y5
10
Y6
11
Y7
12 _Y8
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and}
IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1990, Texas Instruments Incorporated
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