SM470R1B1M-HT_15 Datasheet, PDF (1/79 Pages) Texas Instruments – 16-/32-Bit RISC Flash Microcontroller

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SM470R1B1M-HT
SPNS155I – SEPTEMBER 2009 – REVISED JUNE 2015
SM470R1B1M-HT 16-/32-Bit RISC Flash Microcontroller
1 Device Overview
1.1 Features
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• High-Performance Static CMOS Technology
• SM470R1x 16-/32-Bit RISC Core ( ARM7TDMI™)
– 60-MHz System Clock (Pipeline Mode)
– Independent 16-/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
• Integrated Memory
– 1MB Program Flash
• Two Banks With 16 Contiguous Sectors
– 64KB Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
• Operating Features
– Low-Power Modes: STANDBY and HALT
– Industrial Temperature Range
• 470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– Interrupt Expansion Module (IEM)
– System Integrity and Failure Detection
– ICE Breaker
• Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
• Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock
Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
• Twelve Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Three Serial Communication Interfaces (SCIs)
• 2²⁴ Selectable Baud Rates
• Asynchronous/Isosynchronous Modes
– Two High-End CAN Controllers (HECC)
• 32-Mailbox Capacity
• Fully Compliant With CAN Protocol, Version
2.0B
– Five Inter-Integrated Circuit (I²C) Modules
• Multi-Master and Slave Interfaces
• Up to 400 Kbps (Fast Mode)
• 7- and 10-Bit Address Capability
• High-End Timer Lite (HET)
– 12 Programmable I/O Channels:
• 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
• 64-Instruction Capacity
• External Clock Prescale (ECP) Module
– Programmable Low-Frequency External Clock
(CLK)
• 12-Channel, 10-Bit Multi-Buffered ADC (MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55-µs Minimum Sample and Conversion Time
– Calibration Mode and Self-Test Features
• Flexible Interrupt Handling
• Expansion Bus Module (EBM)
– Supports 8- and 16-Bit Expansion Bus Memory
Interface Mappings
– 42 I/O Expansion Bus Pins
• 46 Dedicated General-Purpose I/O (GIO) Pins and
47 Additional Peripheral I/Os
• Sixteen External Interrupts
• On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1 ⁽¹⁾ (JTAG) Test-Access Port
• Available in KGD, HFQ, HKP, and PGE Packages
(1) The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.