SCANSTA111 Datasheet, PDF (1/38 Pages) National Semiconductor (TI) – Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port

SCANSTA111
www.ti.com
SNLS060K – AUGUST 2001 – REVISED APRIL 2013
SCANSTA111 Enhanced SCAN Bridge
Multidrop Addressable IEEE 1149.1 (JTAG) Port
Check for Samples: SCANSTA111
FEATURES
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•2 True IEEE 1149.1 Hierarchical and Multidrop
Addressable Capability
• The 7 Slot Inputs Support Up to 121 Unique
Addresses, an Interrogation Address,
Broadcast Address, and 4 Multi-Cast Group
Addresses (Address 000000 is Reserved)
• 3 IEEE 1149.1-Compatible Configurable Local
Scan Ports
• Mode Register₀ Allows Local TAPs to be
Bypassed, Selected for Insertion Into the Scan
Chain Individually, or Serially in Groups of
Two or Three
• Transparent Mode can be Enabled with a
Single Instruction to Conveniently Buffer the
Backplane IEEE 1149.1 Pins to those on a
Single Local Scan Port
• LSP ACTIVE Outputs Provide Local Port
Enable Signals for Analog Busses Supporting
IEEE 1149.4.
• General Purpose Local Port Pass-Through Bits
are Useful for Delivering Write Pulses for
FPGA Programming or Monitoring Device
Status.
• Known Power-Up State
• TRST on All Local Scan Ports
• 32-Bit TCK Counter
• 16-Bit LFSR Signature Compactor
• Local TAPs can become TRI-STATE via the OE
Input to Allow an Alternate Test Master to Take
Control of the Local TAPs (LSP_0-2 Have a TRI-
STATE Notification Output)
• 3.0-3.6V V_CC Supply Operation
• Power-Off High Impedance Inputs and Outputs
• Supports Live Insertion/Withdrawal
DESCRIPTION
The SCANSTA111 extends the IEEE Std. 1149.1 test
bus into a multidrop test bus environment. The
advantage of a multidrop approach over a single
serial scan chain is improved test throughput and the
ability to remove a board from the system and retain
test access to the remaining modules. Each
SCANSTA111 supports up to 3 local IEEE 1149.1
scan rings which can be accessed individually or
combined serially. Addressing is accomplished by
loading the instruction register with a value matching
that of the Slot inputs. Backplane and inter-board
testing can easily be accomplished by parking the
local TAP Controllers in one of the stable TAP
Controller states via a Park instruction. The 32-bit
TCK counter enables built in self test operations to be
performed on one port while other scan chains are
simultaneously tested.
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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