SCANPSC100F Datasheet, PDF (1/28 Pages) Fairchild Semiconductor – Embedded Boundary Scan Controller (IEEE 1149.1 Support)

OBSOLETE
SCANPSC100F
www.ti.com
SNOS134D – SEPTEMBER 1998 – REVISED APRIL 2013
SCANPSC100F Embedded Boundary Scan Controller
(IEEE 1149.1 Support)
Check for Samples: SCANPSC100F
FEATURES
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•23 Compatible with IEEE Std. 1149.1 (JTAG) Test
Access Port and Boundary Scan Architecture
• Supported by Texas Instruments SCAN Ease
(Embedded Application Software Enabler)
Software
• Uses Generic, Asynchronous Processor
Interface; Compatible with a Wide Range of
Processors and PCLK Frequencies
• Directly Supports Up to Two 1149.1 Scan
Chains
• 16-bit Serial Signature Compaction (SSC) at
the Test Data In (TDI) Port
• Automatically Produces Pseudo-Random
Patterns at the Test Data Out (TDO) Port
• Fabricated on FACT™ 1.5 μm CMOS Process
• Supports 1149.1 Test Clock (TCK) Frequencies
up to 25 MHz
• TTL-Compatible Inputs; Full-Swing CMOS
Outputs with 24 mA Source/Sink Capability
• Standard Microcircuit Drawing (SMD)
5962-9475001
DESCRIPTION
The SCANPSC100F is designed to interface a
generic parallel processor bus to a serial scan test
bus. It is useful in improving scan throughput when
applying serial vectors to system test circuitry and
reduces the software overhead that is associated with
applying serial patterns with a parallel processor. The
'PSC100F operates by serializing data from the
parallel bus for shifting through the chain of 1149.1
compliant components (i.e., scan chain). Scan data
returning from the scan chain is placed on the parallel
port to be read by the host processor. Up to two scan
chains can be directly controlled with the 'PSC100F
via two independent TMS pins. Scan control is
supplied with user specific patterns which makes the
'PSC100F protocol-independent. Overflow and
underflow conditions are prevented by stopping the
test clock. A 32-bit counter is used to program the
number of TCK cycles required to complete a scan
operation within the boundary scan chain or to
complete a 'PSC100F Built-In Self Test (BIST)
operation. SCANPSC100F device drivers and 1149.1
embedded test application code are available with
TI's SCANEase software tools.
Connection Diagrams
Figure 1. 28-Pin CDIP and CLGA
Figure 2. Pin Assignment for LCCC
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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