SCAN92LV090_15 Datasheet, PDF (1/19 Pages) Texas Instruments – SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

SCAN92LV090
www.ti.com
SNLS058I – SEPTEMBER 2000 – REVISED APRIL 2013
SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN
Check for Samples: SCAN92LV090
FEATURES
1
•2 IEEE 1149.1 (JTAG) Compliant
• Bus LVDS Signaling
• Low Power CMOS Design
• High Signaling Rate Capability (Above 100
Mbps)
• 0.1V to 2.3V Common Mode Range for V_ID =
200mV
• ±100 mV Receiver Sensitivity
• Supports Open and Terminated Failsafe on
Port Pins
• 3.3V Operation
• Glitch Free Power Up/Down (Driver & Receiver
Disabled)
• Light Bus Loading (5 pF Typical) per Bus
LVDS Load
• Designed for Double Termination Applications
• Balanced Output Impedance
• Product Offered in 64 Pin LQFP Package and
NFBGA Package
• High Impedance Bus Pins on Power Off (V_CC =
0V)
DESCRIPTION
The SCAN92LV090A is one in a series of Bus LVDS
transceivers designed specifically for the high speed,
low power proprietary backplane or cable interfaces.
The device operates from a single 3.3V power supply
and includes nine differential line drivers and nine
receivers. To minimize bus loading, the driver outputs
and receiver inputs are internally connected. The
separate I/O of the logic side allows for loop back
support. The device also features a flow through pin
out which allows easy PCB routing for short stubs
between its pins and the connector.
The driver translates 3V TTL levels (single-ended) to
differential Bus LVDS (BLVDS) output levels. This
allows for high speed operation, while consuming
minimal power with reduced EMI. In addition, the
differential signaling provides common mode noise
rejection of ±1V.
The receiver threshold is less than ±100 mV over a
±1V common mode range and translates the
differential Bus LVDS to standard (TTL/CMOS)
levels.
This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture
with the incorporation of the defined boundary-scan
test logic and test access port consisting of Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select
(TMS), Test Clock (TCK), and the optional Test Reset
(TRST).
SIMPLIFIED FUNCTIONAL DIAGRAM
D_IN
D
DE
D0+/RI+
BLVDS I/O
D0-/RI-
ROUT
RE
R
Channel 1 of 9
TDI
TDO
TCK
TMS
TRST
Common to all
data channels
IEEE 1149.1 (JTAG)
Test Access Port
Figure 1.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated