SCAN921023_13 Datasheet, PDF (1/25 Pages) Texas Instruments – SCAN921023 and SCAN921224 20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST

SCAN921023, SCAN921224
www.ti.com
SNLS133D – JAN 2001 – REVISED APRIL 2013
SCAN921023 and SCAN921224 20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
with IEEE 1149.1 (JTAG) and at-speed BIST
Check for Samples: SCAN921023, SCAN921224
FEATURES
1
•2 IEEE 1149.1 (JTAG) Compliant and At-Speed
BIST Test Mode
• Clock Recovery From PLL Lock to Random
Data Patterns
• Ensured Transition Every Data Transfer Cycle
• Chipset (Tx + Rx) Power Consumption < 500
mW (typ) @ 66 MHz
• Single Differential Pair Eliminates Multi-
Channel Skew
• Flow-Through Pinout for Easy PCB Layout
• 660 Mbps Serial Bus LVDS Data Rate (at 66
MHz Clock)
• 10-bit Parallel Interface for 1 Byte Data Plus 2
Control Bits
• Synchronization Mode and LOCK Indicator
• Programmable Edge Trigger on Clock
• High Impedance on Receiver Inputs when
Power is Off
• Bus LVDS Serial Output Rated for 27Ω Load
• Small 49-Lead NFBGA Package
DESCRIPTION
The SCAN921023 transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed
Bus LVDS serial data stream with embedded clock.
The SCAN921224 receives the Bus LVDS serial data
stream and transforms it back into a 10-bit wide
parallel data bus and recovers parallel clock. Both
devices are compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture
with the incorporation of the defined boundary-scan
test logic and test access port consisting of Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select
(TMS), Test Clock (TCK), and the optional Test Reset
(TRST). IEEE 1149.1 features provide the designer or
test engineer access to the backplane or cable
interconnects and the ability to verify differential
signal integrity to enhance their system test strategy.
The pair of devices also features an at-speed BIST
mode which allows the interconnects between the
Serializer and Deserializer to be verified at-speed.
The SCAN921023 transmits data over backplanes or
cable. The single differential pair data path makes
PCB design easier. In addition, the reduced cable,
PCB trace count, and connector size tremendously
reduce cost. Since one output transmits clock and
data bits serially, it eliminates clock-to-data and data-
to-data skew. The powerdown pin saves power by
reducing supply current when not using either device.
Upon power up of the Serializer, you can choose to
activate synchronization mode or allow the
Deserializer to use the synchronization-to-random-
data feature. By using the synchronization mode, the
Deserializer will establish lock to a signal within
specified lock times. In addition, the embedded clock
ensures a transition on the bus every 12-bit cycle.
This eliminates transmission errors due to charged
cable conditions. Furthermore, you may put the
SCAN921023 output pins into TRI-STATE to achieve
a high impedance state. The PLL can lock to
frequencies between 20 MHz and 66 MHz.
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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