PCI4515A Datasheet, PDF (1/6 Pages) Texas Instruments – Single Socket CardBus Controller with Integrated 1394a-2000 OHCI One-Port PHY/Link-Layer Controller

PCI4515A
www.ti.com
SLLA241 – JUNE 2006
Single Socket CardBus Controller with Integrated 1394a-2000 OHCI One-Port
PHY/Link-Layer Controller
FEATURES
• PC Card Standard 8.1 Compliant
• PCI Bus Power Management Interface
Specification 1.1 Compliant
• Advanced Configuration and Power Interface
(ACPI) Specification 2.0 Compliant
• PCI Local Bus Specification Revision 2.3
Compliant
• PC 98/99 and PC2001 Compliant
• Windows Logo Program 2.0 Compliant
• PCI Bus Interface Specification for
PCI-to-CardBus Bridges
• 1.5-V Core Logic and 3.3-V I/O Cells With
Internal Voltage Regulator to Generate 1.5-V
Core V_CC
• Universal PCI Interfaces Compatible With
3.3-V and 5-V PCI Signaling Environments
• Supports PC Card or CardBus With Hot
Insertion and Removal
• Supports 132-MBPS Burst Transfers to
Maximize Data Throughput on Both the PCI
Bus and the CardBus
• Supports Serialized IRQ With PCI Interrupts
• Programmable Multifunction Terminals
• Many Interrupt Modes Supported
• Serial ROM Interface for Loading Subsystem
ID and Subsystem Vendor ID
• ExCA-Compatible Registers Are Mapped in
Memory or I/O Space
• Intel 82365SL-DF Register Compatible
• Supports Ring Indicate, SUSPEND, and PCI
CLKRUN Protocols and PCI Bus Lock (LOCK)
• Provides VGA/Palette Memory and I/O, and
Subtractive Decoding Options, LED Activity
Terminals
• Fully Interoperable With FireWire™ and
i.LINK™ Implementations of IEEE Std 1394
• Compliant With Intel Mobile Power Guideline
2000
• Fully Compliant With Provisions of IEEE Std
1394-1995 for a High-Performance Serial Bus
and IEEE Std 1394a-2000
• Fully Compliant With 1394 Open Host
Controller Interface Specification 1.1
• Full IEEE Std 1394a-2000 Support Includes:
Connection Debounce, Arbitrated Short
Reset, Multispeed Concatenation, Arbitration
Acceleration, Fly-by Concatenation, And Port
Disable/Suspend/Resume
• Power-Down Features to Conserve Energy in
Battery-Powered Applications Include:
Automatic Device Power Down During
Suspend, PCI Power Management for
Link-Layer, and Inactive Ports Powered
Down, Ultralow-Power Sleep Mode
• A IEEE Std 1394a-2000 Fully Compliant Cable
Port at 100M Bits/s, 200M Bits/s, and 400M
Bits/s
• Cable Port Monitors Line Conditions for
Active Connection to Remote Node
• Cable Power Presence Monitoring
• Separate Cable Bias (TPBIAS) for the Port
• Physical Write Posting of Up To Three
Outstanding Transactions
• PCI Burst Transfers and Deep FIFOs to
Tolerate Large Host Latency
• External Cycle Timer Control for Customized
Synchronization
• Extended Resume Signaling for Compatibility
With Legacy DV Components
• PHY-Link Logic Performs System
Initialization and Arbitration Functions
• PHY-Link Encode and Decode Functions
Included for Data-Strobe Bit Level Encoding
• PHY-Link Incoming Data Resynchronized to
Local Clock
• Low-Cost 24.576-MHz Crystal Provides
Transmit and Receive Data at 100M Bits/s,
200M Bits/s, and 400M Bits/s
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Inc..
i.LINK is a trademark of Sony Corporation of America..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated